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ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary ddr sdram registered module 184pin registered module based on 512mb c-die with 72-bit ecc revision 0.0 september. 2004 66 tsop-ii and 60 ball fbga with pb-free (rohs compliant)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary revision history revision 0.0 (september, 2004) - first release
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary samsung electronics co., ltd. reserves the right to change products and specif ications without notice. ordering information operating frequencies part number density organization component composition height m312l6523cus-cb3/a2/b0 512mb 64m x 72 64mx8( k4h510838c) * 9ea 1,200mil m312l2923cus-cb3/a2/b0 1gb 128m x 72 64mx8( k4h510838c) * 18ea 1,200mil m312l2920cus-cb3/a2/b0 1gb 128m x 72 128mx4( k4h510438c) * 18ea 1,200mil m312l5628cu0-ca2/b0 2gb 256m x 72 st.256mx4( k4h1g0638c) * 18ea 1,200mil m312l6523cz0-ccc/b3/a2/b0 512mb 64mx72 64mx8( k4h510838c) * 9ea 1,125mil m312l2923cz0-ccc/b3/a2/b0 1gb 128m x 72 64mx8( k4h510838c) * 18ea 1,125mil m312l2920cz0-ccc/b3/a2/b0 1gb 128m x 72 128mx4( k4h510438c) * 18ea 1,125mil m312l5720cz0-ccc/b3/a2/b0 2gb 256m x 72 128mx4( k4h510438c) * 36ea 1,200mil cc(ddr400@cl=3) b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) speed @cl2 - 133mhz 133mhz 100mhz speed @cl2.5 166mhz 166mhz 133mhz 133mhz speed @cl3 200mhz - - - cl-trcd-trp 3-3-3 2.5-3-3 2-3-3 2.5-3-3 184pin registered dimm ba sed on 512mb c-die (x4, x8) feature ? vdd : 2.5v 0.2v, vddq : 2.5v 0.2v for ddr266, 333 ? vdd : 2.6v 0.1v, vddq : 2.6v 0.1v for ddr400 ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe [dq] (x4,x8) & [l(u)dqs] (x16) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency : ddr266(2, 2.5 clock), ddr333(2.5 cl ock), ddr400(3 clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us re fresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? sstl_2 interface ? 66pin tsop ii and 60 ball fbga pb-free package ? rohs compliant
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary pin configuration (front side/back side) note : 1. * : these pins ar e not used in this module. 2. pins 111, 158 are nc for 1row module & used for 2row module. 3. pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : dm (x8 base module) or dqs (x4 base module). pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc /reset vss dq8 dq9 dqs1 vddq *ck1 */ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 cb0 cb1 vdd dqs8 a0 cb2 vss cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd */cs2 dq48 dq49 vss *ck2 */ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0/dqs9 dq6 dq7 vss nc nc nc vddq dq12 dq13 dm1/dqs10 vdd dq14 dq15 cke1 vddq *ba2 dq20 a12 vss dq21 a11 dm2/dqs11 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3/dqs12 a3 dq30 vss dq31 cb4 cb5 vddq ck0 /ck0 vss dm8/dqs17 a10 cb6 vddq cb7 vss dq36 dq37 vdd dm4/dqs13 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /ras dq45 vddq /cs0 /cs1 dm5/dqs14 vss dq46 dq47 */cs3 vddq dq52 dq53 *a13 vdd dm6/dqs15 dq54 dq55 vddq nc dq60 dq61 vss dm7/dqs16 dq62 dq63 vddq sa0 sa1 sa2 vddspd pin description pin name function pin name function a0 ~ a12 address input (multiplexed) dm0 ~ dm8 data - in mask ba0 ~ ba1 bank select address vdd power supply (2.5v for ddr266/333, 2.6v for ddr400) dq0 ~ dq63 data input/output vddq power supply for dqs (2.5v for ddr266/333, 2.6v for ddr400) dqs0 ~ dqs17 data strobe input/output vss ground ck0,ck0 ~ ck2, ck2 clock input vref power supply for reference cke0, cke1(for double banks) clock enable input vddspd serial eeprom power/supply ( 2.3v to 3.6v ) cs0 , cs1 (for double banks) chip select input sda serial data i/o ras row address strobe scl serial clock cas column address strobe sa0 ~ 2 address in eeprom we write enable nc no connection cb0 ~ cb7 check bit(data-in/data-out) key key
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary 512mb, 64m x 72 ecc module (m312l6523cus) (populated as 1 bank of x8 ddr sdram module) functional block diagram v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd spd d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 6 i/o 5 i/o 3 i/o 1 i/o 7 i/o 4 i/o 2 i/o 0 i/o 0 i/o 2 i/o 5 i/o 6 i/o 1 i/o 3 i/o 4 i/o 7 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 7 i/o 4 i/o 2 i/o 0 i/o 6 i/o 5 i/o 3 i/o 1 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 6 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 3 i/o 1 dqs8 dm8 dm/ cs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 i/o 5 i/o 4 i/o 2 i/o 0 i/o 7 i/o 6 i/o 3 i/o 1 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. pll* ck0,ck0 pck ras cas cke0 ba0-ba1 a0-a12 r e g i s t e r cs0 pck reset rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : sdrams dq0 - d8 a0 -a12 : sdrams d0 - d8 ras : sdrams d0 - d8 cas : sdrams d0 - d8 cke : sdrams d0 - d8 we : sdrams d0 - d8 we * wire per clock loading table/wiring diagrams
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary 1gb, 128m x 72 ecc module (m312l2923cus) (populated as 2 bank of x8 ddr sdram module) functional block diagram rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 6 i/o 5 i/o 3 i/o 1 i/o 7 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 2 i/o 1 i/o 6 i/o 4 i/o 3 i/o 0 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 7 i/o 4 i/o 2 i/o 0 i/o 6 i/o 5 i/o 3 i/o 1 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 6 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 3 i/o 1 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 rcs 1 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 1 i/o 2 i/o 4 i/o 6 i/o 0 i/o 3 i/o 5 i/o 7 i/o 0 i/o 2 i/o 5 i/o 6 i/o 1 i/o 3 i/o 4 i/o 7 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 0 i/o 3 i/o 5 i/o 7 i/o 1 i/o 2 i/o 4 i/o 6 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 1 i/o 3 i/o 5 i/o 7 i/o 0 i/o 2 i/o 4 i/o 6 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp dqs8 dm8 dm/ cs dqs d8 i/o 5 i/o 4 i/o 2 i/o 0 i/o 7 i/o 6 i/o 3 i/o 1 dm/ cs dqs d17 i/o 2 i/o 3 i/o 5 i/o 7 i/o 0 i/o 1 i/o 4 i/o 6 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 pck ras cas cke0 cke1 cs1 ba0-ba1 a0-a12 cs0 we pck reset rcs1 rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe rcke1 ba0 -ba1 : sdrams dq0 - d17 a0 -a12 : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d8 cke : sdrams d9 - d17 we : sdrams d0 - d17 r e g i s t e r pll* ck0,ck0 * wire per clock loading table/wiring diagrams notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms.
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary 1gb, 128m x 72 ecc module (m312l2920cus) (populated as 1 bank of x4 ddr sdram module) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm resistors: 22 ohms. ras cas cke0 ba0-ba1 a0-a12 s0 rs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : sdrams dq0 - d17 a0 -a12 : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d17 we : sdrams d0 - d17 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 cs dm vss dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d10 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d11 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d12 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d13 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d14 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d16 cs dm dqs10 reset pck pck we pll* ck0,ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref strap: see note 4 v ddspd spd (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) functional block diagram
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm0/dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm4/dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm7/dqs16 rcs 0 rcs 1 dqs4 dqs1 dqs5 dqs2 dqs3 dm6/dqs15 dqs6 dqs7 dq15 dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d10 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d11 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d12 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d13 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d14 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d16 dm dm1/dqs10 v ss dqs i/o 3 i/o 2 i/o 1 i/o 0 d18 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d19 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d20 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d21 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d22 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d23 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d24 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d25 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 dm notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. ra0 - ra12 a0-an: sdrams d0 - d35 ras : sdrams d0 - d35 rcas cas : sdrams d0 - d35 rcke1 cke: sdrams d18 - d35 pck we : sdrams d0 - d35 rcke0 rba0 - rba1 ba0-ban: sdrams d0 - d35 ras cas cke0 cke1 rcs1 cs1 ba0-ba1 a0-a12 r e g i s t e r rras rwe cs0 rcs0 we pck reset cke: sdrams d0 - d17 pll ck0,ck0 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d35 d0 - d35 v dd /v ddq d0 - d35 d0 - d35 vref v ddspd spd 2gb, 256m x 72 ecc module [ m312l5628cu0 ] (populated as 2 bank of x4 ddr sdram module) functional block diagram cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dm8/dqs17 dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d17 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d26 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d35 dm cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 2 i/o 4 i/o 7 d0 dm0 i/o 3 i/o 1 i/o 6 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm7 rcs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs dm6 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 cs dqs dqs dqs dqs dqs pck ras cas cke0 ba0-ba1 a0-a12 r e g i s t e r cs0 pck reset rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : ddr sdrams d0 - d8 a0 -a12 : ddr sdrams d0 - d8 ras : ddr sdrams d0 - d8 cas : ddr sdrams d0 - d8 cke : ddr sdrams d0 - d8 we : ddr sdrams d0 - d8 we pll* ck0,ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss ddr sdrams d0 - d8 v dd /v ddq ddr sdrams d0 - d8 ddr sdrams d0 - d8 vref v ddspd spd notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 512mb, 64m x 72 ecc module (m312l6523cz0) (populated as 1 bank of x8 ddr sdram module) functional block diagram dm2 dqs2 dm3 dqs3 dm8 dqs8 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 0 i/o 2 i/o 4 i/o 7 i/o 3 i/o 1 i/o 6 i/o 5 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 0 i/o 2 i/o 4 i/o 7 i/o 3 i/o 1 i/o 6 i/o 5 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary 1gb, 128m x 72 ecc module (m312l2923cz0) (populated as 2 bank of x8 ddr sdram module) functional block diagram rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 rcs 1 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp dqs8 dm8 dm/ cs dqs d8 dm/ cs dqs d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 pck ras cas cke0 cke1 cs1 ba0-ba1 a0-a12 cs0 we pck reset rcs1 rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe rcke1 ba0 -ba1 : ddr sdram dq0 - d17 a0 -a12 : ddr sdram d0 - d17 ras : ddr sdram d0 - d17 cas : ddr sdram dq0 - d17 cke : ddr sdram d0 - d8 cke : ddr sdram d9 - d17 we : ddr sdram d0 - d17 r e g i s t e r pll* ck0,ck0 * wire per clock loading table/wiring diagrams notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary 1gb, 128m x 72 ecc module (m312l2920cz0) (populated as 1 bank of x4 ddr sdram module) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm resistors: 22 ohms. ras cas cke0 ba0-ba1 a0-a12 cs0 rcs0_2 rcs0_1 rba0 - rba1 ra0 - ra12 rras rcas rcke0a rwe rcke0b ba0 -ba1 : ddr sdram dq0 - d17 a0 -a12 :ddr sdram d0 - d17 ras : ddr sdram d0 - d17 cas : ddr sdram dq0 - d17 cke : ddr sdram d0 - d8 cke : ddr sdram d9 - d17 we :ddr sdram d0 - d17 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 cs dm vss dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 cs dm dqs d10 cs dm dqs d11 cs dm dqs d12 cs dm dqs10 reset pck pck we pll* ck0,ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) functional block diagram i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 dqs d13 cs dm dqs d14 cs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 dqs d15 cs dm dqs d16 cs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 dqs d17 cs dm i/o 0 i/o 1 i/o 2 i/o 3
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 rcs 1 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 dqs d0 cs dm dqs d1 dm dqs d2 dm dqs d3 dm dqs d4 dm dqs d5 dm dqs d6 dm dqs d7 dm dqs10 v ss dqs i/o 0 i/o 1 i/o 2 i/o 3 d18 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d19 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d20 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d21 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d22 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d23 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d24 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d25 dm notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. ra0 - ra12 a0-a12: ddr sdram d0 - d35 ras : ddr sdram d0 - d35 rcas cas : ddr sdram d0 - d35 rcke1 cke: ddr sdram d18 - d35 pck we : ddr sdram d0 - d35 rcke0 rba0 - rba1 ba0-ba1: ddr sdram d0 - d35 ras cas cke0 cke1 rcs1 cs1 ba0-ba1 a0-a12 r e g i s t e r rras rwe cs0 rcs0 we pck reset cke: ddr sdram d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d35 d0 - d35 v dd /v ddq d0 - d35 d0 - d35 vref v ddspd spd 2gb, 256m x 72 ecc module [m312l5720cz0] (populated as 2 bank of x4 ddr sdram module) functional block diagram pll* ck0,ck0 * wire per clock loading table/wiring diagrams cb0 cb1 cb2 cb3 dqs8 dqs d8 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d26 dm cb4 cb5 cb6 cb7 dqs17 (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs dqs d9 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d27 dm cs cs dqs d10 dm dqs d11 dm dqs d12 dm dqs d13 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d28 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d29 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d30 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d31 dm cs cs cs cs cs cs cs cs dqs d14 dm dqs d15 dm dqs d16 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d32 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d33 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d34 dm dqs d17 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d35 dm cs cs cs cs cs cs cs cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd, v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma permanent device damage may occur if abs olute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could af fect device reliability. note : power & dc operating conditions (sstl_2 in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v for ddr266/333) v dd 2.3 2.7 v supply voltage(for device with a nominal v dd of 2.6v for ddr400) v dd 2.5 2.7 v i/o supply voltage(for device with a nominal v dd of 2.5v for ddr266/333) v ddq 2.3 2.7 v i/o supply voltage(for device with a nominal v dd of 2.6v for ddr400) v ddq 2.5 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(hal f strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 1. vref is expected to be equal to 0.5*vddq of the transmitting dev ice, and to track variations in the dc level of same. peak-t o peak noise on vref may not e xceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the diff erence between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire t emper- ature and voltage range, for device drain to s ource voltages from 0.25v to 1.0v. for a given output, it r epresents the maximum difference between pullup and pulldown drivers due to process variat ion. the full variation in the ratio of the maximum to mini - mum pullup and pulldown current will not exceed 1.7 for dev ice drain to source volt ages from 0.1 to 1.0. note :
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary ddr sdram idd spec table (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 1,695 1,355 1,355 ma idd1 1,920 1,580 1,580 ma idd2p 420 345 345 ma idd2f 1,020 770 770 ma idd2q 600 525 525 ma idd3p 645 570 570 ma idd3n 1,110 860 860 ma idd4r 1,965 1,625 1,625 ma idd4w 2,100 1,670 1,670 ma idd5 2,550 2,210 2,210 ma idd6 normal 420 345 345 ma low power 405 330 330 ma optional idd7a 3,900 3,335 3,335 ma m312l6523cus [ (64m x 8) * 9 , 512mb module ] m312l2923cus [ (64m x 8) * 18 , 1gb module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 2,180 1,970 1,970 ma idd1 2,410 2,190 2,190 ma idd2p 590 540 540 ma idd2f 1,415 1,290 1,290 ma idd2q 950 900 900 ma idd3p 1,040 990 990 ma idd3n 1,595 1,470 1,470 ma idd4r 2,450 2,240 2,240 ma idd4w 2,585 2,280 2,280 ma idd5 3,040 2,820 2,820 ma idd6 normal 590 540 540 ma low power 560 510 510 ma optional idd7a 4,390 3,950 3,950 ma
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary ddr sdram idd spec table m312l2920cus [ (128m x 4) * 18 , 1gb module ] m312l5628cu0 [ (st.256m x 4) * 18 , 2gb module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 2,640 2,340 2,340 ma idd1 3,090 2,790 2,790 ma idd2p 465 415 415 ma idd2f 1,290 1,170 1,170 ma idd2q 830 780 780 ma idd3p 920 870 870 ma idd3n 1,470 1,350 1,350 ma idd4r 3,180 2,880 2,880 ma idd4w 3,450 2,970 2,970 ma idd5 4,350 4,050 4,050 ma idd6 normal 465 420 420 ma low power 430 380 380 ma optional idd7a 7,050 6,300 6,300 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 3,610 3,310 3,310 ma idd1 4,060 3,760 3,760 ma idd2p 810 760 760 ma idd2f 2,080 1,960 1,960 ma idd2q 1,530 1,480 1,480 ma idd3p 1,710 1,660 1,660 ma idd3n 2,440 2,320 2,320 ma idd4r 4,150 3,850 3,850 ma idd4w 4,420 3,940 3,940 ma idd5 5,320 5,020 5,020 ma idd6 normal 810 760 760 ma low power 735 685 685 ma optional idd7a 8,020 7,270 7,270 ma
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary ddr sdram idd spec table (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) a2 (ddr266@cl=2) b0 (ddr266@cl=2.5) unit notes idd0 1,790 1,695 1,355 1,355 ma idd1 2,010 1,920 1,580 1,580 ma idd2p 420 420 345 345 ma idd2f 1,020 1,020 770 770 ma idd2q 600 600 525 525 ma idd3p 780 645 570 570 ma idd3n 1,290 1,110 860 860 ma idd4r 2,100 1,965 1,625 1,625 ma idd4w 2,280 2,100 1,670 1,670 ma idd5 2,730 2,550 2,210 2,210 ma idd6 normal 420 420 345 345 ma low power 405 405 330 330 ma optional idd7a 3,990 3,900 3,335 3,335 ma m312l6523cz0 [ (64m x 8) * 9 , 512mb module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) a2 (ddr266@cl=2) b0 (ddr266@cl=2.5) unit notes idd0 2,450 2,180 1,970 1,970 ma idd1 2,680 2,410 2,190 2,190 ma idd2p 590 590 540 540 ma idd2f 1,415 1,415 1,290 1,290 ma idd2q 950 950 900 900 ma idd3p 1,310 1,040 990 990 ma idd3n 1,960 1,595 1,470 1,470 ma idd4r 2,770 2,450 2,240 2,240 ma idd4w 2,950 2,585 2,280 2,280 ma idd5 3,400 3,040 2,820 2,820 ma idd6 normal 590 590 540 540 ma low power 560 560 510 510 ma optional idd7a 4,660 4,390 3,950 3,950 ma m312l2923bg0 [ (64m x 8) * 18 , 1gb module ]
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary ddr sdram idd spec table m312l5720bg0 [ (128m x 4) * 36, 2gb module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) a2 (ddr266@cl=2) b0 (ddr266@cl=2.5) unit notes idd0 4,150 3,610 3,310 3,310 ma idd1 4,600 4,060 3,760 3,760 ma idd2p 810 810 760 760 ma idd2f 2,080 2,080 1,960 1,960 ma idd2q 1,530 1,530 1,480 1,480 ma idd3p 2,250 1,710 1,660 1,660 ma idd3n 3,160 2,440 2,320 2,320 ma idd4r 4,780 4,150 3,850 3,850 ma idd4w 5,140 4,420 3,940 3,940 ma idd5 6,040 5,320 5,020 5,020 ma idd6 normal 810 810 760 760 ma low power 735 735 685 685 ma optional idd7a 8,560 8,020 7,270 7,270 ma m312l2920bg0 [ (128m x 4) * 18 , 1gb module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) a2 (ddr266@cl=2) b0 (ddr266@cl=2.5) unit notes idd0 2,820 2,640 2,340 2,340 ma idd1 3,270 3,090 2,790 2,790 ma idd2p 470 465 415 415 ma idd2f 1,290 1,290 1,170 1,170 ma idd2q 830 830 780 780 ma idd3p 1,190 920 870 870 ma idd3n 1,830 1,470 1,350 1,350 ma idd4r 3,450 3,180 2,880 2,880 ma idd4w 3,810 3,450 2,970 2,970 ma idd5 4,710 4,350 4,050 4,050 ma idd6 normal 465 465 420 420 ma low power 430 430 380 380 ma optional idd7a 7,230 7,050 6,300 6,300 ma
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary note : 1. vid is the magnitude of t he difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same. output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq input/output capacitance (ta= 25 c, f=100mhz) parameter symbol m312l6523cus,m312l2920cus m312l2923cus,m312l5720cu0 unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin1 9 11 9 11 pf input capacitance(cke0) cin2 9 11 9 11 pf input capacitance( cs 0) cin3 9 11 9 11 pf input capacitance( clk0, clk0 ) cin411121112pf input capacitance(dm0~dm8) cin5 10 11 14 16 pf data & dqs input/output capacitance(dq0~dq63) cout1 10 11 14 16 pf data input/output capacitance (cb0~cb7) cout2 10 11 14 16 pf parameter symbol m312l6523cz0,m312l2920cz0 m312l2923cz0,m312l5720cz0 unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin1 9 11 9 11 pf input capacitance(cke0) cin2 9 11 9 11 pf input capacitance( cs 0) cin3 9 11 9 11 pf input capacitance( clk0, clk0 ) cin411121112pf input capacitance(dm0~dm8) cin5 10 11 13 15 pf data & dqs input/output capacitance(dq0~dq63) cout1 10 11 13 15 pf data input/output capacitance (cb0~cb7) cout2 10 11 13 15 pf ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dq s and dm signals vih(ac) vref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary ac timming parameters & specifications parameter symbol cc (ddr400@cl=3.0) b3 (ddr333@cl=2.5) a2 (ddr266@cl=2.0) b0 (ddr266@cl=2.5) unit note min max min max min max min max row cycle time trc 55 60 65 65 ns refresh row cycle time trfc 70 72 75 75 ns row active time tras 40 70k 42 70k 45 120k 45 120k ns ras to cas delay trcd 15 18 20 20 ns row precharge time trp 15 18 20 20 ns row active to row active delay trrd 10 12 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read commandtwtr2111tck clock cycle time cl=2.0 tck - - 7.5 12 7.5 12 10 12 ns cl=2.5 6 12 6 12 7.5 12 7.5 12 ns cl=3.0 510------ clock high level width tch 0.45 0 .550.450.550.450.550.450.55tck clock low level width tcl 0.45 0. 55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.55 +0.55 -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck tac -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to ouput data edge tdqsq - 0.4 - 0.45 - 0.5 - 0.5 ns 22 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.72 1 .250.751.250.751.250.751.25tck dqs-in setup time twpres0000ns13 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck address and control input set up time(fast) tis 0.6 0.75 0.9 0.9 ns 15, 17~19 address and control input hold time(fast) tih 0.6 0.75 0.9 0.9 ns 15, 17~19 address and control input setup tis 0.7 0.8 1.0 1.0 ns 16~19 address and control input hold time(slow) tih 0.7 0.8 1.0 1.0 ns 16~19 data-out high impedence time from ck/ck thz - +0.65 - +0.7 - +0.75 - +0.75 ns 11 data-out low impedence time from ck/ck tlz -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11 mode register set cycle time tmrd 10 12 15 15 ns dq & dm setup time to dqs tds 0.4 0.45 0.5 0.5 ns j, k dq & dm hold time to dqs tdh 0.4 0.45 0.5 0.5 ns j, k control & address input pulse width tipw 2.2 2.2 2.2 2.2 ns 18 dq & dm input pulse widt h tdipw 1.75 1.75 1.75 1.75 ns 18 exit self refresh to non-read command txsnr 75 75 75 75 ns exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 14 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs -ns21 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -ns20, 21 data hold skew factor tqhs 0.5 0.55 0.75 0.75 ns 21 dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 12 active to read wi th auto precharge command trap 15 18 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 23
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary system characteristics for ddr sdram the following specification parameters are required in s ystems using ddr333, ddr266 & ddr200 devices to ensure proper system performance. these charac teristics are for system simulation purposes and are guaranteed by design. table 1 : input slew rate for dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate table 4 : input/output setup & hold derating for rise/fall delta slew rate table 5 : output slew rate char acteristice (x4, x8 devices only) table 6 : output slew rate characteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics ac characteristics ddr333 ddr266 ddr200 parameter symbol min max min max min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew tbd tbd tbd tbd 0.5 4.0 v/ns a, m input slew rate ? tis ? tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate ? tds ? tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k delta slew rate ? tds ? tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr266b ddr200 parameter min max min max notes output slew rate matching ratio (pullup to pulldown) tbd tbd 0.67 1.5 e,m
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary b. pulldown slew rate is measured under the test conditions shown in figure 3. output test point vddq 50 ? figure 3 : pulldown slew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met fo r any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. the remaining dq bits re main the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.5v(for ddr266/ 333) and 2.6v(for ddr400), typical process minimum : 70 c (t ambient), vddq = 2.3v(f or ddr266/333) and 2.5v(for dd r400), slow - slow process maximum : 0 c (t ambient), vddq = 2.7v(f or ddr266/333) and 2.7v(for dd r400), fast - fast process e. the ratio of pullup slew rate to pulld own slew rate is specified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maxi mum difference between pullup and pulldown drivers due to process variation. f. verified under typical conditions for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to in crease tis and tih in the case where t he input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesser of the slew rates det emined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. j. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise , fall rate and dc-dc delta rise, input slew rate is based on the lesser of the slew rates determined by either vi h(ac) to vil(ac) or vih(dc) to vil( dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase td s and tdh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is bas ed on the lesser of the slew rate s deter mined by either vih(ac) to vil(ac) or vih(dc ) to vil(dc), and simila rly for rising transitions. m. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotonic. system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 2. output test point vssq 50 ? figure 2 : pullup slew rate test load
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9 a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address (a0~a9, a11,a12) read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down mode entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functi ons are same as the cbr refresh of dram. the automatical prechar ge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row acti ve and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row acti ve and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row ac tive and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row ac tive and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/writ e command can not be issued. another bank read/wr ite command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop co mmand is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no o peration(nop)" in ddr sdram.
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8 ddr sdram, tsopii sdram part no : k4h510838c a b reg pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) (30.48 +/-0.15) 1.2 +/-0.06 5.077 (128.950) 0.393 (10.00) (19.80) 0.78 (17.80) 0.7 0.10 m cba r (2.00) 0.0787 (3.00 min) 0.118 min reg 0.157 max 0.050 0.0039 (1.270 0.10) (3.99 max) (4.00) (0.157) physical dimensions : 64m x 72 (m312l6523cus) 0.050 0.0078 0.006 (0.20 0.15) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 m b 0.100 (2.30) 2.500 +0.1/-0.0
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8, 128mx4 ddrsdram, tsopii sdram part no. : k4h510838c, k4h510438c a b reg pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) 5.077 (128.950) 0.393 (10.00) (19.80) 0.78 (17.80) 0.7 0.10 m cba r (2.00) 0.0787 reg 0.157 max 0.050 0.0039 (1.270 0.10) (3.99 max) (4.00) (0.157) physical dimensions: 128mx72 (m312 l2923cus), 128mx72 (m312l2920cus) (30.48 +/-0.15) 1.2 +/-0.06 (3.00 min) 0.118 min 0.050 0.0078 0.006 (0.20 0.15) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 m b 0.100 (2.30) 2.500 +0.1/-0.0
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is st. 256mx4 sdram, 66tsopii sdram part no : k4h1g0638c a b pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) 5.077 (128.950) 0.393 (10.00) (19.80) 0.78 (17.80) 0.7 0.10 m cba r (2.00) 0.0787 reg. 0.268 max 0.050 0.0039 (1.270 0.10) (6.81 max) (4.00) (0.157) physical dimensions: st .256mx72 (m312l5628cu0) (30.48 +/-0.15) 1.2 +/-0.06 (3.00 min) 0.118 min 0.100 (2.30) 2.500 +0.1/-0.0 0.050 0.0078 0.006 (0.20 0.15) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 m b
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8 ddr sdram, fbga ddr sdram part no. : k4h510838c-z***, physical dimensions: 64mx72 (m312l6523cz0) 133.35 a 128.95 a 2x 3.00 min w1 4x 4.00+/-0.1 v1 64.77 p2 49.53 p3 120.65 p1 19.80 b1 28.575 +/-0.15 b 6.35 a b 10.00 b2 1 92 detail b detail a 3.80 w x1 x2 6.35 x 2.175 4.175 v 1.80 d 1.0 +/-0.05 0.20 +/-0.15 t 2.50 g e 1.27 max 0.178 d1 units : millimeters 2.99 max 12.00 184 93 1.27 +/-0.1 2x dia. 2.50 +0.1/-0.00 n
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8, 128mx4 ddr sdram, fbga ddr sdram part no. : k4h 510838c-z***, k4h510438c-z*** physical dimensions: 128mx72 (m312l2923cz0), (m312l2920cz0) 133.35 a 128.95 a 2x 3.00 min w1 4x 4.00+/-0.1 v1 64.77 p2 49.53 p3 120.65 p1 19.80 b1 28.575 +/-0.15 b 6.35 a b 10.00 b2 1 92 detail b detail a 3.80 w x1 x2 6.35 x 2.175 4.175 v 1.80 d 1.0 +/-0.05 0.20 +/-0.15 t 2.50 g e 1.27 max 0.178 d1 units : millimeters 184 93 3.99 max 12.00 1.27 +/-0.1 2x dia. 2.50 +0.1/-0.00 n
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 0.0 sept ember, 2004 preliminary tolerances : 0.005(.13) unless otherwise specified the used device is 128mx4 ddr sdram, fbga ddr sdram part no : k4h510438c-z*** physical dimensions: 256mx72 (m312l5720cz0) units : millimeters 133.35 a 128.95 a 2x 3.00 min w1 4x 4.00+/-0.1 v1 64.77 p2 49.53 p3 120.65 p1 19.80 b1 30.48 +/-0.15 b 6.35 a b 10.00 b2 1 92 detail b detail a 3.80 w x1 x2 6.35 x 2.175 4.175 v 1.80 d 1.0 +/-0.05 0.20 +/-0.15 t 2.50 +/-0.2 g e 1.27 max 0.178 d1 3.99 max 12.0 10.0 184 93 1.27 +/-0.1 2x dia. 2.50 +0.1/-0.00 n

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